PHLEGM v8 Checkpoint 54 - SPC700 bit-memory operations and flag-safe branching

Evidence: ActRaiser SNES-NTSC coredumps captured October 10, 2026 10:29 MST.
SPC700 driver executes 783 instructions / 2624 cycles then explicitly traps
at PC=$0413 on opcode $A2. Opcode $A2 is SPC700 SET1 $dp.5.
The main 5A22 CPU remains polling $9A63, INIDISP=$80 forced blank.

Changes: Implement all 8 SET1 dp.bit and 8 CLR1 dp.bit opcode programs,
using existing generic FETCH8/DIRECT/READ8/OR/AND/WRITE8 primitives.
Rewrite all 8 BBS and 8 BBC definitions to use bitmasked temporary values
and existing BNZ primitive. No processor status flag is modified, whether
or not the branch is taken. Previously, taken bit branches skipped PS restore.
This also removes scratch PS save/restore from these instructions.

All behavior is defined in spc700-opcodes.config.phlegm and loaded/compiled
at runtime on machine load or session restore. No modifications to generic
microcode.lib or SNES native CPU opcode dispatch. Unknown SPC700 instructions
continue to TRAP; S-SMP timers and DSP synthesis remain incomplete.

Validation: 256 unique opcode rows; valid/illegal/undocumented classification;
valid generic numeric operations, 3072-operation capacity; model-checked
all SET1, CLR1, BBS and BBC across both P flags, random byte values,
positive/negative relative displacements, flag preservation.
Native FreeBASIC compilation and running ActRaiser remain unverified.
